1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device such as, for example, an insulated gate type field effect transistor and especially a high-power vertical MOSFET.
2. Description of the Related Art
In recent years, vertical power MOSFETs prepared using a single crystal of silicon carbide have been used as power transistors. In order to reduce the occurrence of loss in the power transistor, it is necessary to reduce the ON resistance. For this purpose, a trench gate type power MOSFET, as shown in FIG. 16, has been proposed as a device capable of effectively reducing the ON resistance (for example, Japanese Unexamined Patent Publication (Kokai) No. 4-239778). In the trench gate type power MOSFET shown in FIG. 16, an n type epitaxial layer 22 is provided on an n type silicon carbide semiconductor substrate 21, a p type epitaxial layer 23 is provided on the n type epitaxial layer 22 and an n type source region 24 is provided in the p type epitaxial layer 23 in a predetermined region. Further, a trench 25 is provided which extends through the n type source region 24 and the p type epitaxial layer 23 into the n type epitaxial layer 22. A gate electrode 27 is provided on the gate insulating layer 26 within the trench 25. An insulating layer 28 is provided on the upper surface of the gate electrode 27, a source electrode 29 is formed on the n type source region 24 including the surface of the insulating layer 28, and a drain electrode 30 is formed on the surface of the n type silicon carbide semiconductor substrate 21.
In this case, a channel through which a carrier is allowed to flow between the source terminal and the drain terminal has been formed by applying a voltage to the gate electrode 27 to produce an electric field in the gate insulating layer 26 sandwiched between the gate electrode 27 and the p type epitaxial layer 23 in the side wall portion of the trench 25, thereby reversing the conductivity type of the p type epitaxial layer 23 in contact with the gate insulating layer 26.
A vertical power MOSFET, as shown in FIG. 17, which induces a channel by an accumulation mode has been proposed as a device which can be prepared using single crystal silicon carbide and is capable of reducing the ON resistance (U.S. Pat. No. 5,323,040). The vertical power MOSFET shown in FIG. 17 is constructed as follows. An n.sup.+ type drain region 33 is formed on a first surface 32a of a silicon carbide semiconductor substrate 31, and an n type silicon carbide semiconductor drift region 34 is provided more inward than the n.sup.+ type drain region 33. An n.sup.+ type source region 35 is provided on a second surface 32b of the silicon carbide semiconductor substrate 31, and an n.sup.- type silicon carbide semiconductor channel region 36 is provided between the n.sup.+ type source region 35 and the n.sup.- type silicon carbide semiconductor drift region 34. Further, a trench 37 which extends into the n.sup.- type silicon carbide semiconductor drift region 34 is provided on the second surface 32b of the silicon carbide semiconductor substrate 31, thus providing a mesa region 38 including the n.sup.+ type source region 35 and the n.sup.- type silicon carbide semiconductor channel region 36. An insulating layer 39 is provided along the side face 37a of the trench 37 and the bottom face 37b of the trench 37. The trench 37 is filled with a gate electrode 40. A source electrode 41 and a drain electrode 42 are provided respectively on the n.sup.+ source region 35 and the n.sup.+ type drain region 33.
In this case, carrier conduction between the source terminal and the drain terminal has been conducted by applying a positive voltage to the gate electrode 40 to create an n type accumulation layer channel 43 in the vicinity of the side face 37a in the n.sup.- type silicon carbide semiconductor channel region 36. The work function of the gate electrode 40, the impurity concentration of the n.sup.- type silicon carbide semiconductor channel region 36, and the width W of the mesa region 38 are designed so that the mesa region 38 is depleted when no voltage is applied to the gate electrode 40. Therefore, when no voltage or a negative voltage is applied to the gate electrode 40, carrier conduction is less likely to occur between the source terminal and the drain terminal.
Thus, in the vertical power MOSFET shown in FIG. 17, induction using a channel accumulation mode lowers the threshold voltage, and reduction in size of the unit cell 44 (reduction in width W of the mesa region 38 to about 2 .mu.m) increases the integration to lower the ON resistance.
In the trench gate type power MOSFET shown in FIG. 16, the impurity concentration of the region where the channel is formed has been specified by the impurity concentration of the p type epitaxial layer 23. This poses the following problems. The concentration N.sub.A of impurities in the p type epitaxial layer 23 and the distance (thickness) a between the source region 24 and the n type epitaxial layer 22 are among parameters determining the blocking voltage across the source and the drain of the power MOSFET shown in FIG. 16. The blocking voltage across the source and drain is governed by avalanche conditions for pn junction between the p type epitaxial layer 23 and the n type epitaxial layer 22 and conditions under which the p type epitaxial layer 23 is depleted to create punch-through. For this reason, the impurity concentration N.sub.A of the p type epitaxial layer 23 should be satisfactorily high, and the thickness a should also be satisfactorily large. Increasing the impurity concentration N.sub.A of the p type epitaxial layer 23 unfavorably results in increased gate threshold voltage. Further, this increases scattering of the impurities and, hence, lowers the channel mobility, unfavorably increasing the ON resistance. On the other hand, increasing the thickness a increases the channel length, unfavorably increasing the ON resistance.
Thus, in order to realize a power MOSFET having high blocking voltage, low current loss during operation, and low threshold voltage, the impurity concentration of the p type epitaxial layer should be regulated independently of the impurity concentration of the region where the channel is formed. However, it is difficult to attain this by the conventional structure and production process.
Lowering the concentration of the channel forming layer by thermal diffusion has been used, in the trench gate type power MOSFET using single crystal silicon, as one means to solve the above problem. In the trench gate type power MOSFET using silicon carbide, however, the coefficient of the thermal diffusion of impurity atoms in silicon carbide is very small, posing a new problem in that the thermal diffusion cannot be used.
Further, in the vertical MOSFET shown in FIG. 17, since the breakdown of the device is determined by the blocking voltage of the insulating layer in the bottom face of the trench, the blocking voltage is lower than that of devices wherein the blocking voltage is determined by the avalanche breakdown of the pn junction. Further, during OFF state of the transistor, under high temperature conditions, a large number of carriers are supplied from the n.sup.+ type source region 35 to the n.sup.- type silicon carbide semiconductor region 36, unfavorably creating a high leakage current between the source and the drain.
When the trench 25 is formed by dry etching, damage to the channel formed face occurs by ion etching, deteriorating the MOS interface properties and, hence, deteriorating the MOS switching properties.